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19-2757; Rev 0; 1/03
670MHz LVDS-to-LVDS and Anything-to-LVDS 2:1 Multiplexers
General Description
The MAX9176/MAX9177 are 670MHz, low-jitter, lowskew 2:1 multiplexers ideal for protection switching, loopback, and clock distribution. The devices feature ultra-low 68ps peak-to-peak deterministic jitter that ensures reliable operation in high-speed links that are highly sensitive to timing errors. The MAX9176 has fail-safe LVDS inputs and an LVDS output. The MAX9177 has "anything" differential inputs (CML/LVDS/LVPECL) and an LVDS output. The output can be put into high impedance using the power-down input. The MAX9176 features fail-safe circuits that drive the output high when a selected input is open, undriven and shorted, or undriven and terminated. The MAX9177 has bias circuits that force the output high when a selected input is open. The mux select and powerdown inputs are compatible with standard LVTTL/ LVCMOS logic. The select and power-down inputs tolerate undershoot of -1V and overshoot of V CC + 1V. The MAX9176/ MAX9177 are available in 10-pin MAX and 10-lead thin QFN packages, and operate from a single 3.3V supply over the -40C to +85C temperature range. o 1.0ps(RMS) Jitter (max) at 670MHz o 68ps(P-P) Jitter at 800Mbps Data Rate o 3.3V Supply o LVDS Fail-Safe Inputs (MAX9176) o Anything Inputs (MAX9177) Accept CML/LVDS/LVPECL o Select and Power-Down Inputs Tolerate -1.0V and VCC + 1.0V o Low-Power CMOS Design o 10-Lead MAX and QFN Packages o -40C to +85C Operating Temperature Range o Conform to ANSI TIA/EIA-644 LVDS Standard o IEC61000-4-2 Level 4 ESD Rating
Features
MAX9176/MAX9177
Applications
Protection Switching Loopback Clock Distribution
PART MAX9176EUB MAX9176ETB* MAX9177EUB MAX9177ETB*
Ordering Information
TEMP RANGE -40C to +85C -40C to +85C -40C to +85C -40C to +85C PIN-PACKAGE 10 MAX 10 Thin QFN-EP** 10 MAX 10 Thin QFN-EP**
Functional Diagram appears at end of data sheet.
*Future product--contact factory for availability. **EP = Exposed paddle.
Pin Configurations
TOP VIEW
IN0+ 1 INOGND IN1+ IN12 3 4 5 MAX 10 OUT+ 9 OUTVCC PD SEL IN0+ 1 INOGND IN1+ IN12 3 4 5 EXPOSED PAD 10 OUT+ 9 8 7 6 OUTVCC PD SEL
MAX9176
8 7 6
QFN (LEADS UNDER PACKAGE)
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
670MHz LVDS-to-LVDS and Anything-to-LVDS 2:1 Multiplexers MAX9176/MAX9177
ABSOLUTE MAXIMUM RATINGS
VCC to GND ...........................................................-0.3V to +4.0V IN_+, IN_- to GND .................................................-0.3V to +4.0V OUT+, OUT- to GND .............................................-0.3V to +4.0V PD, SEL to GND .........................................-1.4V to (VCC + 1.4V) Single-Ended and Differential Output Short-Circuit Duration (OUT+, OUT-) ......................Continuous Continuous Power Dissipation (TA = +70C) 10-Pin MAX (derate 5.6mW/C above +70C) ............444mW 10-Lead Thin QFN (derate 24.4mW/C above +70C)..1951mW Operating Temperature Range ...........................-40C to +85C Maximum Junction Temperature .....................................+150C Storage Temperature Range .............................-65C to +150C ESD Protection Human Body Model (RD = 1.5k, CS = 100pF) (IN_+, IN_-, OUT+, OUT-) ...............................................+16kV IEC61000-4-2 Level 4 (RD = 330, CS = 150pF) Contact Discharge (IN_+, IN_-, OUT+, OUT-).................+8 kV Air-Gap Discharge (IN_+, IN_-, OUT+, OUT-)................+15kV Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VCC = 3.0V to 3.6V, RL = 100, PD = high, SEL = high or low, differential input voltage |VID| = 0.05V to 1.2V, MAX9176 input common-mode voltage VCM = |VID/2| to 2.4V - |VID/2|, MAX9177 input common-mode voltage VCM = |VID/2| to VCC - |VID/2|, TA = -40C to +85C, unless otherwise noted. Typical values are at VCC = 3.3V, |VID| = 0.2V, VCM = 1.25V, TA = +25C.) (Notes 1, 2, 3)
PARAMETER Differential Input High Threshold Differential Input Low Threshold Input Current SYMBOL VTH VTL IIN+, IINFigure 1 MAX9176 Power-Off Input Current IINO+, IINOVCC = 0 or open, Figure 1 VIN+ = 3.6V or 0, VIN- = 3.6V or 0, VCC = 0 or open, Figure 1 -20 +20 A -50 -20 +20 CONDITIONS MIN TYP MAX +50 UNITS mV mV A DIFFERENTIAL INPUTS (IN_+, IN_-)
MAX9177
Fail-Safe Input Resistors (MAX9176) Input Resistors (MAX9177) Input Capacitance LVTTL/LVCMOS INPUTS (SEL, PD) Input High Voltage Input Low Voltage Input Current LVDS OUTPUT (OUT+, OUT-) Differential Output Voltage Change in Differential Output Voltage Between Logic States Offset Voltage
RIN1 RIN2 RIN3 CIN VIH VIL
VCC = 3.6V, 0 or open, Figure 1 VCC = 3.6V, 0 or open, Figure 1 IN_+ or IN_- to GND (Note 4)
60 200 212
108 394 450 4.5
k k pF V V mA A mA mV mV V
2.0 -1.0 -1.0V SEL, PD 0V -1.5 -20 0V SEL, PD VCC VCC SEL, PD VCC + 1.0V
VCC + 1.0 +0.8 +20 +1.5
IIN
VOD VOD VOS
Figure 2 Figure 2 Figure 3
250
393 1.0
475 15 1.375
1.125
1.25
2
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670MHz LVDS-to-LVDS and Anything-to-LVDS 2:1 Multiplexers
DC ELECTRICAL CHARACTERISTICS (continued)
(VCC = 3.0V to 3.6V, RL = 100, PD = high, SEL = high or low, differential input voltage |VID| = 0.05V to 1.2V, MAX9176 input common-mode voltage VCM = |VID/2| to 2.4V - |VID/2|, MAX9177 input common-mode voltage VCM = |VID/2| to VCC - |VID/2|, TA = -40C to +85C, unless otherwise noted. Typical values are at VCC = 3.3V, |VID| = 0.2V, VCM = 1.25V, TA = +25C.) (Notes 1, 2, 3)
PARAMETER Change in Offset Voltage Between Logic States Fail-Safe Differential Output Voltage (MAX9176) Differential Output Resistance Power-Down Single-Ended Output Current SYMBOL VOS VOD RDIFF Figure 3 Figure 2 VCC = 3.6V or 0 VOUT+ = open, VOUT- = 3.6V or 0 VOUT- = open, VOUT+ = 3.6V or 0 PD, SEL = low, VCC = 0 or open VOUT+ = open, VOUT- = 3.6V or 0 VOUT- = open, VOUT+ = 3.6V or 0 -15 250 95 CONDITIONS MIN TYP 4 393 123 MAX 15 475 146 UNITS mV mV
MAX9176/MAX9177
IPD
PD = low
-1.0
0.01
+1.0
A
Power-Off Single-Ended Output Current
IOFF
-1.0
0.01
+1.0
A
Output Short-Circuit Current Differential Output Short-Circuit Current Magnitude Supply Current Power-Down Supply Current Output Capacitance
IOS IOSD ICC ICCPD CO
VID = +50mV or -50mV, VOUT+ = 0 or VCC VID = +50mV or -50mV, VOUT- = 0 or VCC VID = +50mV or -50mV, VOD = 0 (Note 4) RL = 100, PD = VCC, SEL = VCC or 0 RL = 100, PD = 0, other inputs open OUT+ or OUT- to GND (Note 4)
+15 15 26 0.5 40 20 5.2
mA mA mA A pF
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670MHz LVDS-to-LVDS and Anything-to-LVDS 2:1 Multiplexers MAX9176/MAX9177
AC ELECTRICAL CHARACTERISTICS
(VCC = 3.0V to 3.6V, RL = 100, CL = 5pF, differential input voltage |VID| = 0.15V to 1.2V, MAX9176 input common-mode voltage VCM = |VID/2| to 2.4V - |VID/2|, MAX9177 input common-mode voltage VCM = |VID/2| to VCC - |VID/2|, TA = -40C to +85C, unless otherwise noted. Typical values are at VCC = 3.3V, |VID| = 0.2V, VCM = 1.25V, TA = +25C.) (Notes 5, 6, 7)
PARAMETER High-to-Low Propagation Delay Low-to-High Propagation Delay Added Deterministic Jitter Added Random Jitter Pulse Skew tPLH - tPHL Part-to-Part Skew Rise Time Fall Time Select to Out Delay Power-Down Time Power-Up Time Maximum Data Rate Maximum Switching Frequency Switching Supply Current PRBS Supply Current SYMBOL tPHL tPLH tDJ tRJ tSKP tSKPP1 tSKPP2 tR tF tPSO tPD tPU DRMAX fMAX ICCSW ICCPR Figures 4, 5 Figures 4, 5 Figures 4, 5 (Notes 8, 12) Figures 4, 5 (Note 12) Figures 4, 5 Figures 4, 5 (Note 9) Figures 4, 5 (Note 10) Figures 4, 5 Figures 4, 5 Figure 6 Figures 7, 8 Figures 7, 8 Figures 4, 5, VOD 250mV (Note 11) Figures 4, 5, VOD 250mV (Note 11) fIN = 670MHz fIN = 155MHz DR = 800Mbps, 223 - 1 PRBS input 800 670 38 26 27 58 47 49 217 157 320 340 2.0 CONDITIONS MIN 1.33 1.33 TYP 2.46 2.49 68 0.7 27 0.4 MAX 3.23 3.31 80 1.0 142 1.3 2.0 383 360 2.7 6.0 35 UNITS ns ns ps(P-P) ps(RMS) ps ns ps ps ns ns s Mbps MHz mA mA DIFFERENTIAL INPUTS (IN_+, IN_-)
Note 1: Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground except VTH, VTL, VID, VOD, and VOD. Note 2: Maximum and minimum limits over temperature are guaranteed by design and characterization. Devices are 100% tested at TA = +25C. Note 3: Tolerance on all external resistors (including figures) is 1%. Note 4: Guaranteed by design and characterization. Note 5: AC parameters are guaranteed by design and characterization and not production tested. Limits are set at 6 sigma. Note 6: CL includes scope probe and test jig capacitance. Note 7: Pulse-generator output for differential inputs IN_+, IN_- (unless otherwise noted): f = 670MHz, 50% duty cycle, RO = 50, tR = 500ps, and tF = 500ps (0% to 100%). Pulse-generator output for single-ended inputs PD, SEL: tR = tF = 1.5ns (0.2VCC to 0.8VCC), 50% duty cycle, VOH = VCC + 1.0V settling to VCC, VOL = -1.0V settling to zero. Note 8: Pulse-generator output for tDJ: VOD = 0.15V, VOS = 1.25V, bit rate = 800Mbps, 223 - 1 PRBS, RO = 50, tR = 500ps, and tF = 500ps (0% to 100%). Note 9: tSKPP1 is the magnitude of the difference of any differential propagation delays between devices operating under identical conditions. Note 10: tSKPP2 is the magnitude of the difference of any differential propagation delays between devices operating over rated conditions. Note 11: Meets all AC specifications. Note 12: Input jitter subtracted from output jitter.
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670MHz LVDS-to-LVDS and Anything-to-LVDS 2:1 Multiplexers MAX9176/MAX9177
VCC VCC RIN2 COMPARATOR IN_+ RIN1 IN_+ VCC 0.3V TO MUX IN_RIN1 LVDS RCVR IN_RIN3 TO MUX RIN3
MAX9176 FAIL-SAFE INPUT
MAX9177 INPUT
Figure 1. Input Structure
1.25V 1.20V 1.25V 1.20V
IN_+
OUT+ VOD RL
5k VTEST = 0 TO VCC 5k
PULSE GENERATOR 50
IN_+ IN_-
OUT+ OUTCL CL RL
5k VTEST = 0 TO VCC 5k
IN_-
OUT-
50
Figure 2. VOD Test Circuit
Figure 4. Transition Time and Propagation Delay Test Circuit
IN_OUT+ 1.25V 1.20V 1.25V 1.20V IN_IN_+ IN_+ RL/2 OUTRL/2 VOS OUTOUT+ VOS = ((VOUT+) + (VOUT-))/2 80% 0 (OUT+) - (OUT)20% tR tF 80% 0 20% VODtPLH tPHL
VOD+
Figure 3. VOS Test Circuit
Figure 5. Transition Time and Propagation Delay Timing
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670MHz LVDS-to-LVDS and Anything-to-LVDS 2:1 Multiplexers MAX9176/MAX9177
IN0VID = -0.2V INO+ IN1+ VID = +0.2V IN1VCC + 1.0V VCC 0.5 VCC SEL tPSO OUTtPSO 0.5 VCC 0 -1.0V GENERATOR 50 GND PD OUT5pF OUT1.25V 1.25V 1.20V 1.25V 1.20V IN_+ IN_VCC OUT+ 5pF 50
OUT+
MAX9176 MAX9177
50
OUT+
Figure 6. Select-to-Out Delay Timing
Figure 7. Power-Up/Down Delay Test Circuit
1.0V + VCC VCC PD 0.5VCC 0V -1.0V tPD OUT+ WHEN VID = +50mV OUT- WHEN VID = -50mV OUT+ WHEN VID = -50mV OUT- WHEN VID = +50mV 50% tPD tPU 50% tPU VOH 50% 1.25V 1.25V 50% VOL
Figure 8. Power-Up/Down Delay Waveform
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670MHz LVDS-to-LVDS and Anything-to-LVDS 2:1 Multiplexers
Typical Operating Characteristics
((MAX9176) VCC = 3.3V, |VID| = 0.2V, VCM = 1.25V, RL = 100, CL = 5pf, PD = VCC, SEL = 0V, IN1+, IN1- = open, TA = +25C, unless otherwise noted.)
SUPPLY CURRENT vs. TEMPERATURE
MAX9176 toc01
MAX9176/MAX9177
DIFFERENTIAL OUTPUT VOLTAGE vs. FREQUENCY
DIFFERENTIAL OUTPUT VOLTAGE (mV)
MAX9176 toc02
OUTPUT RISE/FALL TIME vs. TEMPERATURE
MAX9176 toc03
45
700 600 500 400 300 200
450
40 SUPPLY CURRENT (mA)
400 RISE/FALL TIME (ps) tR
35
350
30
300 tF 250
25 fIN = 155MHz 20 -40 -15 10 35 60 85 TEMPERATURE (C)
100 fIN = 155MHz 0 0 100 200 300 400 500 600 700 800 FREQUENCY (MHz) 200 -40 -15 10 35 60 85 TEMPERATURE (C)
DIFFERENTIAL PROPAGATION DELAY vs. TEMPERATURE
DIFFERENTIAL PROPAGATION DELAY (ns)
MAX9176 toc04
SUPPLY CURRENT vs. FREQUENCY
MAX9176 toc05
SUPPLY CURRENT vs. DATA RATE
MAX9176 toc06
3.00 2.75 2.50 tPLH 2.25 tPHL 2.00 1.75 1.50 -40 -15 10 35 60
50
50
SUPPLY CURRENT (mA)
30
SUPPLY CURRENT (mA)
40
40
30
20
20 PRBS 2 - 1
23
10 85 0 100 200 300 400 500 600 700 800 FREQUENCY (MHz) TEMPERATURE (C)
10 0 100 200 300 400 500 600 700 800 FREQUENCY (Mbps)
DC SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX9176 toc07
OUTPUT RISE/FALL TIME vs. SUPPLY VOLTAGE
MAX9176 toc08
DIFFERENTIAL PROPAGATION DELAY vs. SUPPLY VOLTAGE
DIFFERENTIAL PROPAGATION DELAY (ns)
MAX9176 toc09
28
395 fIN = 155MHz OUTPUT RISE/FALL TIME (ps) 375 355 335 315 tR 295 275 tF
3.0 2.8 2.5 2.3 2.0 1.8 fIN = 155MHz 1.5
DC SUPPLY CURRENT (mA)
27
tPLH
26
25
tPHL
24
23 3.0 3.1 3.2 3.3 3.4 3.5 3.6 SUPPLY VOLTAGE (V)
3.0
3.1
3.2
3.3
3.4
3.5
3.6
3.0
3.1
3.2
3.3
3.4
3.5
3.6
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
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670MHz LVDS-to-LVDS and Anything-to-LVDS 2:1 Multiplexers MAX9176/MAX9177
Typical Operating Characteristics (continued)
((MAX9176) VCC = 3.3V, |VID| = 0.2V, VCM = 1.25V, RL = 100, CL = 5pf, PD = VCC, SEL = 0V, IN1+, IN1- = open, TA = +25C, unless otherwise noted.)
DC DIFFERENTIAL OUTPUT VOLTAGE vs. LOAD RESISTOR
MAX9176 toc10
DIFFERENTIAL PROPAGATION DELAY vs. COMMON-MODE VOLTAGE
DIFFERENTIAL PROPAGATION DELAY (ns)
MAX9176 toc11
600 DC DIFFERENTIAL OUTPUT VOLTAGE (mV)
3.00 2.88 2.75 2.63 2.50 2.38 tPHL (MAX9176) 2.25 fIN = 155MHz 2.13 tPLH (MAX9176) tPLH, tPHL (MAX9177)
500
400
300
200
100 50 70 90 110 130 150 LOAD RESISTOR ()
0.1
0.5
0.9
1.3
1.7
2.0
2.4
2.8
3.2
COMMON-MODE VOLTAGE (V)
Pin Description
PIN MAX 1 2 3 4 5 6 7 8 9 10 -- QFN 1 2 3 4 5 6 7 8 9 10 EP NAME IN0+ IN0GND IN1+ IN1SEL PD VCC OUTOUT+ Exposed Pad Noninverting Differential Input 0 Inverting Differential Input 0 Ground Noninverting Differential Input 1 Inverting Differential Input 1 LVTTL/LVCMOS Input Select. SEL = high selects differential input 1. SEL = low selects differential input 0. Internal pulldown resistor to GND. LVTTL/LVCMOS Input. Device is powered down when PD is low. Internal pulldown resistor to GND. Power Supply Inverting Differential Output Noninverting Differential Output Exposed Pad. Solder to ground. FUNCTION
8
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670MHz LVDS-to-LVDS and Anything-to-LVDS 2:1 Multiplexers MAX9176/MAX9177
Table 1. Function Table
INPUTS (IN_+) - (IN_-) +50mV -50mV -50mV < VID < +50mV MAX9177 MAX9176 Open Open, undriven short, or undriven parallel termination H OUTPUT (OUT+) - (OUT-) H L Indeterminate X L or open
Table 2. Input Select and Power-Down Function Table
SEL H L or open PD H H OUT+, OUTIN1+, IN1IN0+, IN0High impedance to ground and 123 (typ) differential output resistance
Detailed Description
The MAX9176/MAX9177 are 670MHz, low-jitter, lowskew 2:1 multiplexers ideal for protection switching, loopback, and clock distribution. The devices feature ultra-low 68ps(P-P) deterministic jitter that ensures reliable operation in high-speed links that are highly sensitive to timing error. The MAX9176 has fail-safe LVDS inputs and an LVDS output. The MAX9177 has anything differential inputs (CML/LVDS/LVPECL) and an LVDS output. The output can be put into high impedance using the power-down input. The MAX9176 features fail-safe circuits that drive the output high when a selected input is open, undriven and shorted, or undriven and terminated. The MAX9177 has bias circuits that force the output high when a selected input is open. The mux select and power-down inputs are compatible with standard LVTTL/LVCMOS logic. The select and power-down inputs tolerate undershoot of -1V and overshoot of V CC + 1V. The MAX9176/ MAX9177 are available in 10-pin MAX and 10-lead thin QFN packages, and operate from a single 3.3V supply over the -40C to +85C temperature range.
age is smaller. See the Differential Output Voltage vs. Load Resistance curve in Typical Operating Characteristics for more information. The output is short-circuit current limited for single-ended and differential shorts.
MAX9176 Input Fail-Safe
The fail-safe feature of the MAX9176 sets the output high when the differential input is: * Open * Undriven and shorted * Undriven and terminated Without a fail-safe circuit, when the selected input is undriven, noise at the input may switch the output and it may appear to the system that data is being sent. Open or undriven terminated input conditions can occur when a cable is disconnected or cut, or when the driver output is in high impedance. A shorted input can occur because of a cable failure. When the selected input is driven with a differential signal of VID= 50mV to 1.2V within a voltage range of 0 to 2.4V, the fail-safe circuit is not activated. If the selected input is open, undriven and shorted, or undriven and terminated, an internal resistor in the fail-safe circuit pulls both inputs above VCC - 0.3V, activating the failsafe circuit and forcing the output high (Figure 1).
Current-Mode LVDS Output
The LVDS output uses a current-steering configuration. This approach results in less ground bounce and less output ringing, enhancing noise margin and system speed performance. A differential output voltage is produced by steering current through the parallel combination of the integrated differential output resistor and transmission line impedance/termination resistor. When driving a 100 load, a differential voltage of 250mV to 475mV is produced. For loads greater than 100, the output voltage is larger, and for loads less than 100, the output volt-
Overshoot and Undershoot Voltage Protection
The MAX9176/MAX9177 are designed to protect the select and power-down inputs (SEL and PD) against latchup due to transient overshoot and undershoot voltage. If the input voltage goes above V CC or below GND by up to 1V, an internal circuit limits input current to 1.5mA.
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670MHz LVDS-to-LVDS and Anything-to-LVDS 2:1 Multiplexers MAX9176/MAX9177
Applications Information
Power-Supply Bypassing
Bypass the VCC pin with high-frequency surface-mount ceramic 0.1F and 0.001F capacitors in parallel as close to the device as possible, with the smaller valued capacitor closest to VCC. and single-ended logic signals is recommended. Separate the differential signals from the logic signals with power and ground planes for best results.
IEC 61000-4-2 Level 4 ESD Protection
The IEC 61000-4-2 standard (Figure 10) specifies ESD tolerance for electronic systems. The IEC61000-4-2 model specifies a 150pF capacitor that is discharged into the device through a 330 resistor. The MAX9176/ MAX9177 differential inputs and outputs are rated for IEC61000-4-2 level 4 (8kV Contact Discharge and 15kV Air-Gap Discharge). The Human Body Model (HBM, Figure 9) specifies a 100pF capacitor that is discharged into the device through a 1.5k resistor. IEC 61000-4-2 level 4 discharges higher peak current and more energy than the HBM due to the lower series resistance and larger capacitor.
Differential Traces
Input and output trace characteristics affect the performance of the MAX9176/MAX9177. Use controlledimpedance differential traces (100 typical). To reduce radiated noise and ensure that noise couples as common mode, route the differential input and output signals within a pair close together. Reduce skew by matching the electrical length of the two signal paths that make up the differential pair. Excessive skew can result in a degradation of magnetic field cancellation. Maintain a constant distance between the differential traces to avoid discontinuities in differential impedance. Minimize the number of vias to further prevent impedance discontinuities.
RC 1M CHARGE-CURRENT LIMIT RESISTOR HIGHVOLTAGE DC SOURCE
RD 1.5k DISCHARGE RESISTANCE DEVICE UNDER TEST
Cables and Connectors
Interconnect for LVDS typically has a controlled differential impedance of 100. Use cables and connectors that have matched differential impedance to minimize impedance discontinuities. Avoid the use of unbalanced cables such as ribbon or simple coaxial cable. Balanced cables such as twisted pair offer superior signal quality and tend to generate less EMI due to magnetic field canceling effects. Balanced cables pick up noise as common mode, which is rejected by the LVDS receiver.
Cs 100pF
STORAGE CAPACITOR
Termination
The MAX9176/MAX9177 require external input and output termination resistors. For LVDS, connect an input termination resistor across each differential input and at the far end of the interconnect driven by the LVDS output. Place the input termination resistor as close to the receiver input as possible. Termination resistors should match the differential impedance of the transmission line. Use 1% surface-mount resistors. The MAX9176/MAX9177 feature an integrated differential output resistor. This resistor reduces jitter by damping reflections produced by any mismatch between the transmission line and termination resistor at the far end of the interconnect.
Figure 9. Human Body Test Model
RC 50 TO 100 CHARGE-CURRENT LIMIT RESISTOR HIGHVOLTAGE DC SOURCE
RD 330 DISCHARGE RESISTANCE DEVICE UNDER TEST
Cs 150pF
STORAGE CAPACITOR
Board Layout
Separate the differential and single-ended signals to reduce crosstalk. A four-layer printed circuit board with separate layers for power, ground, differential signals,
10
Figure 10. IEC 61000_4-2 Contact Discharge Test Model
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670MHz LVDS-to-LVDS and Anything-to-LVDS 2:1 Multiplexers
Functional Diagram
IN0+ IN0IN1+ IN1SEL PD
MAX9176/MAX9177
OUT+ OUT-
Chip Information
TRANSISTOR COUNT: 744 PROCESS: CMOS
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670MHz LVDS-to-LVDS and Anything-to-LVDS 2:1 Multiplexers MAX9176/MAX9177
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)
10LUMAX.EPS
1 1
e
10
4X S
10
INCHES MAX DIM MIN 0.043 A 0.006 A1 0.002 A2 0.030 0.037 0.120 D1 0.116 0.118 0.114 D2 0.116 0.120 E1 E2 0.114 0.118 H 0.187 0.199 L 0.0157 0.0275 L1 0.037 REF b 0.007 0.0106 e 0.0197 BSC c 0.0035 0.0078 0.0196 REF S 0 6
MILLIMETERS MAX MIN 1.10 0.15 0.05 0.75 0.95 3.05 2.95 3.00 2.89 3.05 2.95 2.89 3.00 4.75 5.05 0.40 0.70 0.940 REF 0.177 0.270 0.500 BSC 0.090 0.200 0.498 REF 0 6
H y 0.500.1 0.60.1
1
1
0.60.1
TOP VIEW
BOTTOM VIEW
D2 GAGE PLANE A2 A b A1 D1
E2
c
E1 L1
L
FRONT VIEW
SIDE VIEW
PROPRIETARY INFORMATION TITLE:
PACKAGE OUTLINE, 10L uMAX/uSOP
APPROVAL DOCUMENT CONTROL NO. REV.
21-0061
I
12
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670MHz LVDS-to-LVDS and Anything-to-LVDS 2:1 Multiplexers
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) 6, 8, &10L, QFN THIN.EPS
MAX9176/MAX9177
PACKAGE OUTLINE, 6, 8 & 10L, QFN THIN (DUAL), EXPOSED PAD, 3x3x0.80 mm
21-0137
C
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670MHz LVDS-to-LVDS and Anything-to-LVDS 2:1 Multiplexers MAX9176/MAX9177
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)
COMMON DIMENSIONS SYMBOL A D E A1 L k A2 MIN. 0.70 2.90 2.90 0.00 0.20 MAX. 0.80 3.10 3.10 0.05 0.40
0.25 MIN 0.20 REF.
PACKAGE VARIATIONS PKG. CODE T633-1 T833-1 T1033-1 N 6 8 10 D2 1.500.10 1.500.10 1.500.10 E2 2.300.10 2.300.10 2.300.10 e 0.95 BSC 0.65 BSC 0.50 BSC JEDEC SPEC MO229 / WEEA MO229 / WEEC MO229 / WEED-3 b 0.400.05 0.300.05 0.250.05 [(N/2)-1] x e 1.90 REF 1.95 REF 2.00 REF
PACKAGE OUTLINE, 6, 8 & 10L, QFN THIN (DUAL), EXPOSED PAD, 3x3x0.80 mm
21-0137
C
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
14 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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Price & Availability of MAX9176

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